1. Field of the Invention
The present disclosure relates to the field of semiconductor device fabrication, and more particular, to a semiconductor device and its fabrication method.
2. Description of the Related Art
Embedded SiGe (eSiGe) is a process that has been proposed to improve channel stress of a MOS (Metal oxide Semiconductor) device, and increase carrier mobility. In an embedded SiGe (eSiGe) process, the source region and the drain region are formed by eSiGe to apply a stress to the channel region. In order to achieve a better effect, in general, it is necessary to perform recess etching before SiGe epitaxial growth on the source region/drain region. The recess etching forms a Sigma (“Σ”) shaped recess, after which SiGe is epitaxially grown in the Sigma shaped recess. As a result, the effect of the stress application is enhanced and semiconductor device performance is improved.
The SiGe epitaxial growth needs to be sufficiently close to the channel to increase stress; however, in the epitaxial growth, if P-type impurities are in-situ doped at a high concentration from the beginning, the short-channel effect may be intensified.
In order to address the above problem, presently, it is common to epitaxially grow a substantially un-doped layer of SiGe first, followed by the epitaxial growth of high concentration p-type doped SiGe.